1. Field of the Invention
The present invention is related to a memory array, and more particularly, to a memory array having read and/or write assist functions.
2. Description of the Prior Art
FIG. 1 is a diagram illustrating prior art memory cell 102 and pre-charge circuit 104. The memory cell 102 may be a commonly used 6T SRAM (static random access memory) cell and is located in a column of cells of a plurality of columns of cells in a memory array. The pre-charge circuit 104 may be used to pre-charge a pair of bit line BL and bit line bar BLB coupled to the memory cell 102 before a read cycle or a write cycle of the memory array.
FIG. 2 is a waveform diagram of FIG. 1. The horizontal axis of FIG. 2 is time t. From top to bottom of FIG. 2 are word line WL voltage, bit line BL and bit line bar BLB voltages, and storage nodes Na and Nb voltages. If the memory cell 102 is half selected, the bit line BL and the bit line bar BLB are pre-charged to a working voltage VDD before the read cycle by setting a control signal Pre_b to logic low for turning on PMOS transistors PP1 and PP2 of the pre-charge circuit 104. After the bit line BL and the bit line bar BLB are pre-charged to the working voltage VDD, the control signal Pre_b changes to logic high for turning off the PMOS transistors PP1 and PP2, then a word line WL is set to logic high for starting the read cycle. As shown in FIG. 2, either the storage node Na or Node Nb of the half selected memory cell 102 is prone to be disturbed during the read cycle because the bit line BL and the bit line bar BLB are pre-charged to the working voltage VDD, which causes higher divided voltage (Disturb weak point in FIG. 2) at node Na or node Nb. Therefore, how to prevent disturbance in the half selected memory cell 102 during the read cycle is an issue worth exploring.